Xcellon-Flex Combo 10/40GbE Accelerated Performance

Load module model


Number of ports per load module

16 ports of SFP+ 10GbE and 4-ports of QSFP 40GbE

Chassis slots per module


Maximum ports per chassis

XGS12-SD: 192-ports 10GbE SFP+ and 48-ports 40GbE QSFP

XGS12-HS: 192-ports 10GbE SFP+ and 48-ports 40GbE QSFP

XG12 Rackmount (6000W): 192-ports 10GbE SFP+ and 48-ports 40GbE QSFP

XGS2-SD 3U: 32-ports 10GbE SFP+ and 8-ports 40GbE QSFP+

XGS2-HS 3U: 32-ports 10GbE SFP+ and 8-ports 40GbE QSFP+

XM2 Desktop: 16-ports 10GbE SFP+ and 4-ports 40GbE QSFP[1]

SFP+ optical transceivers

(see ordering information)



QSFP optical transceiver

(see ordering information)



Multi-core processor technology


Interface protocols

IEEE802.3ae 10GbE LAN


Data center protocols

(see optional upgrades for DCBX, FCoE, FCF)

FCoE /FIP, LLDP/DCBX, VNTAG/VNIC, VEPA, FabricPath, TRILL, SPBM, OpenFlow, VXLAN, Segment Routing ISIS


Layer 2-3 routing protocol emulation support


Layer 4-7 application traffic testing support


Aggregation capability

Yes (for 10GbE ports)

Capture buffer per port

256MB (10GbE)

1GB (40GbE)

Transmit engine

Wire-speed packet generation with timestamps, sequence numbers, data integrity signature, and packet group signatures

Stream definitions per port


Number of transmit flows per port (sequential values)


Number of transmit flows per port (PGID)

1 million

Table UDF

1 million entries

User defined field features

Fixed, increment, or decrement by user-defined step, value lists, range lists (10GbE only), cascade, random, and chained

Data field per stream

Fixed, increment (byte/word), decrement (byte/word), random, repeating, user-specified

Frame length controls

Fixed, random, weighted random, or increment by user-defined step

Error generation

10GbE: CRC (good/bad/none), undersize, oversize

40GbE: CRC (good/bad), undersize, oversize

IPv4, IPv6, UDP, TCP checksum

Hardware checksum generation and verification

Receive engine

Wire-speed packet filtering, capturing, real-time latency, and inter-arrival time for each packet group, data integrity, and sequence checking

Trackable receive flows

1 million


48-bit source/destination address, 2x128-bit user-definable pattern and offset, frame length range, CRC error, data integrity error, sequence checking error (small, big, reverse)

Statistics and rates

(counter size: 64 bits)

Link state, line speed, frames sent, valid frames received, bytes sent/received, fragments, undersize, oversize, CRC errors, VLAN tagged frames, 6 user-defined stats (UDS), capture trigger (UDS 3), capture filter (UDS 4), 8 QoS counters, data integrity frames, data integrity errors, sequence checking frames, sequence checking errors, ARP, and ping requests and replies

Flow control

IEEE802.03x PAUSE frame control

IEEE802.1Qbb (PFC)

Latency measurements

10GbE: 20ns resolution in packet timestamp

40GbE: 2.5ns resolution in packet timestamp

Link fault signaling at 10GbE

Link state indicator for: No Fault, Local Fault, and Remote Fault

Link fault signaling at 40GbE

Generate local and remote faults with controls for the number of faults and order of faults, plus the ability to select the option to have the transmit port ignore link faults from a remote link partner

Intrinsic latency adjustment

Ability to remove inherent latency from 10GbE/40GbE port electronics when used with MSA-compliant 10GbE/40GbE transceivers

40GbE physical coding sublayer (PCS) test features:

IEEE 802.3ba-compliant PCS transmit and receive side test capabilities

  • Per PCS lane, transmit lane mapping

Supports all combination of PCS lane mapping: Default, Increment, Decrement, Random, and Custom

  • Per PCS lane, skew insertion capability

User-selectable from zero up to 3 microseconds of PCS Lane skew insertion on the transmit side

  • Per PCS lane, lane marker, or lane marker and payload error injections

User-selectable ability to inject errors into the PCS Lane Marker and simultaneously into PCS Lane Marker and Payload fields. This includes the ability to inject sync bit errors into the Lane Marker and Payload. User can control the PCS lane, number or errors, and period count; and manage the repetition of the injected errors.

  • Per PCS lane, receive lanes statistics

PCS Sync Header and Lane Marker Lock, Lane Marker mapping, Relative lane deskew up to 52 microseconds, Sync Header and PCS Lane Marker Error counters, indicators for Loss of Synch Header and Lane Marker, BIP8 errors

Transmit line clock adjustment (10GbE and 40GbE)

Ability to adjust the parts per million (ppm) line frequency over a range of -100 to +100 ppm

Operating temp. range

41°F to 86°F (5°C to 30°C), ambient air temperature

Load module dimensions

16.90” (L) x 12.00” (W) x 1.28” (H)

429mm (L) x 305mm (W) x 33mm (H)


Module only: 11.75 lbs (5.34 kg)

Shipping: 14.05 lbs (6.38 kg)

Application Support

Xcellon-Flex Combo 10/40GbE Accelerated Performance Load Module

IxExplorerTM: layers 1, 2, and 3 wire-speed traffic generation, capture, and analysis.

IxExplorer Tcl API: custom user script development for layer 1-3 testing.

IxNetwork: provides wire-rate traffic generation with service modeling that builds realistic, dynamically-controllable data-plane traffic. IxNetwork offers the industry's best test solution for functional and performance testing by using comprehensive emulation for routing, MPLS, VPLS, high-availability, IP multicast, switching, carrier Ethernet, broadband, and DCB protocols.

IxNetwork Tcl API: custom user script development for layer 2-7 testing.

IxLoad: a scalable solution for testing converged multiplay services, application delivery platforms, and security devices and systems. IxLoad emulates data, voice, and video subscribers and associated protocols to ensure quality of experience (QoE).


[1] The XM2 portable chassis (941-0023) supports up to 1 FlexAP1040SQ load module. No other load module may be installed in the XM2 portable chassis when a FlexAP1040SQ load module is installed.

[2]In the Data Center Bridging mode, the number of transmit streams per port is reduced by one-half to 256 streams for 10GbE and 40GbE ports.

Key Features
  • First 10GE and 40GE test solution to break the terabit barrier with a single rack mount chassis
  • High density 10GE and 40GE test solution: 16x10GE ports and 4x40GE ports per module
  • Aggregation, for ultra-high protocol scale and performance, is supported on multiple 10GE ports on a single load module
  • Data center ready – data center bridging with LLDP/DCBX, FCoE, and priority-based flow control (PFC, IEEE802.1Qbb), OpenFlow, VXLAN protocol support
  • Switches between 10GE or 40GE modes of operation as test plans demand
  • Support for the IxNetwork and IxLoad test applications for Layer 2-7 support

The Xcellon architecture features aggregation of multi-core CPUs and massive memory to meet testing needs for ultra-high scale and performance. This architecture delivers several times the protocol emulation of its nearest competitor and breaks the terabit barrier for 10GE test solutions.

The Xcellon-Flex Combo is the first load module in the test industry to offer both 10GE SFP+ and 40GE QSFP ports in a single chassis slot with high perofrmance L2-7 support. With 16x10GE ports and 4x40GE ports per module, it beats the competition in terms of port density and flexibility. Using aggregation technology to combine CPU power and memory, it provides ultra-high networking protocol scalability: up to several times the performance of its nearest competitor. Processor resources and memory can be aggregated dynamically across groups of 4x10GE ports, creating up to 4 super-ports per module with maximum protocol scalability.

Xcellon-Flex Combo is used in conjunction with Ixia's test applications IxNetwork and IxLoad for Xcellon-Flex is best-in-class for high-performance, L2-7 testing at 10/40GE speeds.

Ixia’s IxNetwork and the Xcellon-Flex load module supports a comprehensive portfolio of routing and service emulations for next-generation network testing.